mitsubishi semiconduct or PS21312 transfer-mold type insula ted type aug. 1999 PS21312 integra ted po wer functions 3rd generation igbt in ver ter br idge f or 3 phase dc-to-a c power con v ersion. applica tion a c200v three-phase in v erter dr iv e f or small po w er motor control. fig. 1 package outlines mitsubishi semiconduct or PS21312 transfer-mold type insula ted type integra ted drive, pr o tection and system contr ol functions ? f or upper-leg igbt s : dr iv e circuit, high v oltage isolated high-speed le v el shifting, control circuit under-voltage (uv) protection. note : bootstr ap supply scheme can be applied. ? f or low er-leg igbt s : dr iv e circuit, control circuit under-v oltage protection (uv), shor t-circuit protection (sc). ? f ault signaling : corresponding to a sc f ault (lo w-side igbt) or a uv f ault (lo w-side igbt). ? input interf ace : 5v line cmos/ttl compatib le , schmitt t r igger receiv er circuit. * note: the v alues used in the abo v e figure are tentativ e . (3.556) (0.5) (1.656) (3.556) (6.25) (0.75) (30.5) (1.778) (1.778 26) (6.25) (6.25) 16 17 18 13 14 1 5 1 0 987 654 321 11 12 19 20 21 22 23 24 35 34 33 32 31 26 25 27 28 29 30 (8) (8) (5) (0.5) (17.4) (17.4) (0.5) (1.25) (2.5) (1.2) (35 ) a (6.5) (10.5) (1) pcb terminal terminal code 1 vufs 2 (upg) 3 vufb 4 vp1 5 (com) 6 up 7 vvfs 8 (vpg) 9 vvfb 10 vp1 11 (com) 12 vp 13 vwfs 14 (wpg) 15 vwfb 16 vp1 17 (com) 18 wp 19 (ung) 20 vno(nc) 21 un 22 vn 23 wn 24 fo 25 cfo 26 cin 27 vnc 28 vn1 29 (wng) 30 (vng) 31 p 32 u 33 v 34 w 35 n p a ttern slit (pcb la y out) (1) (1.9) (0.5) (1.5) (1.8min) (0.5) (1) hea t sink side t ype name , lot no . dummy pin ( f 2 depth 2) ( f 3.3) hea t sink side detail a *note2 (7.62 4) (7.62) (41) (42) (49) (4min) *note1:(***) = dumm y pin. *note 2: in order to increase the surf ace distance betw een ter minals , cut a slit, etc. on the pcb surf ace when mounting a module .
mitsubishi semiconduct or PS21312 transfer-mold type insula ted type aug. 1999 fig. 2 internal functions block diagram (typical application example) fig. 3 external part of the dip-ipm protection circuit note1: in the recommended external protection circuit, please s elect the rc time constant in the range 1.5~2.0 m s. 2: to prevent erroneous protection operation, the wiring of a, b, c should be as short as possible. drive circuit drive circuit protection circuit w v u b c v nc cin a p n1 n c r shunt resistor external protection circuit dip-ipm l-side igbt s h-side igbt s sc protection trip level i c (a) t w ( m s) 2 0 short circuit protective function (sc) : sc protection is achieved by sensing the l-side dc-bus curre nt (through the external shunt resistor) after allowing a suitable filtering time (de fined by the rc circuit). when the sensed shunt voltage exceeds the sc trip-level, all the l-side igbts are turned off and a fault signal (fo) is output. since the sc fault ma y be repetitive, it is recommended to stop the system when the fo signal is receive d and check the fault. collector current waveform z drive circuit cbuC cbu+ cbvC cbv+ cbwC cbw+ (15v line) (5v line) (note 1, 2) v d v nc v nc w ac input ac line output v u input signal coditioning level shifter drive circuit protection circuit (uv) input signal coditioning input signal coditioning input signal conditioning fo logic sc protection prot ec t i on ci rcu i t ( u v ) prot ec t i on ci rcu i t ( u v ) control supply under-voltage protection drive circuit drive circuit f o cfo p n 1 n f o output (5v line) (note 3, 5) high-side input (pwm) (5v line) note 1,2) low-side input (pwm) m (note 6) bootstrap circuit for detailed description of the boot-strap circuit construction, please contact mitsubishi electric dip-ipm c z : surge absorber c : ac filter (ceramic capacitor 2.2~6.5nf) (protection against common-mode noise) c4 c3 c3 : tight tolerance, temp-compensated electrolytic type c4 : 0.22~2 m f r-category ceramic capacitor for noise filtering. (note : the capacitance value depends on the pwm control scheme used in the applied system). note1: to prevent the input signals oscillation, an rc coupling at each input is recommended. (see also fig. 6) 2: by virtue of integrating an application specific type hv ic inside the module, direct coupling to cpu terminals witho ut any opto-coupler or transformer isolation is possible. (see also fig. 6) 3: this output is open collector type. the signal line shou ld be pulled up to the positive side of the 5v power supply with a pproximately 5.1k w resistance. (see also fig. 6) 4: the wiring between the power dc link capacitor and the p /n1 terminals should be as short as possible to protect the dip-ipm against catastrophic high surge voltages. for extra precaution, a smal l film type snubber capacitor (0.1~0.22 m f, high voltage type) is recommended to be mounted close to these p and n1 dc power input terminals. 5: fo output pulse width should be decided by connecting ex ternal capacitor between cfo and v nc terminals. (example : cfo=22nf t fo =1.8ms (typ.)) 6: high voltage diodes (600v or more) should be used in the bootstrap circuit. h-side igbt s l-side igbt s cin (note 4) fig. 3 inrush current limiter circuit level shifter level shifter
mitsubishi semiconductor PS21312 transfer-mold type insulated type aug. 1999 400 e20~+100 e40~+125 1500 v d = 13.5~16.5v, inverter part t j = 125?c, non-repetitive, less than 2 m s (note 2) 60hz, sinusoidal, ac 1 minute, connection pins to heat-sink plate v cc(prot) t f t stg v iso v v v v ma v 20 20 e0.5~+5.5 e0.5~v d +0.5 15 e0.5~v d +0.5 applied between v p1 -v nc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between u p , v p , w p -v nc , u n , v n , w n -v nc applied between f o -v nc sink current at f o terminal applied between cin-v nc control supply voltage control supply voltage input voltage fault output supply voltage fault output current current sensing input voltage v d v db v cin v fo i fo v sc 450 500 600 5 10 20 e20~+150 applied between p-n applied between p-n t c = 25?c t c = 25?c, instantaneous value (pulse) t c = 25?c, per 1 chip (note 1) v cc v cc(surge) v ces i c i cp p c t j condition symbol parameter ratings unit supply voltage supply voltage (surge) collector-emitter voltage each igbt collector current each igbt collector current (peak) collector dissipation junction temperature v v v a a w ?c maximum ratings (t j = 25?c, unless otherwise noted) inverter part condition symbol parameter ratings unit control (protection) part symbol ratings unit self protection supply voltage limit (short-circuit protection capability) heat-fin operation temperature storage temperature isolation voltage v ?c ?c v rms total system note 1 : the maximum junction temperature rating of the power chips integrated within the dip-ipm is 150?c (@ t f 100?c). however, to en- sure safe operation of the dip-ipm, the average junction temperature should be limited to t j(ave) 125?c (@ t f 100?c). parameter condition note 2 : t f measurement point p u v w n c control terminals fwdi chip al board temp. measurement point (inside the al board) 16mm 18mm igbt chip power terminals temp. measurement point (inside the al board) groove al board specifications: dimensions 100 ? 100 ? 10mm, finishing: 12s, warp: ?0~100 m m 100~200 m m of evenly applied silicon-grease igbt/fwdi chip
mitsubishi semiconductor PS21312 transfer-mold type insulated type aug. 1999 13.5 13.5 ? ? ? ? 4.9 ? 0.8 ? 3.0 0.45 10.0 10.5 10.3 10.8 1.0 0.8 2.5 0.8 2.5 ma v t j = 25?c t j = 125?c i c = 5a, t j = 25?c i c = 5a, t j = 125?c v ce(sat) v ec t on t rr t c(on) t off t c(off) i ces condition symbol parameter limits inverter igbt part (per 1/6 module) inverter fwdi part (per 1/6 module) r th(j-f)q r th(j-f)f min. ?c/w thermal resistance typ. max. ? ? ? ? 6.0 6.5 unit t j = 25?c, ei c = 5a, v cin = 5v condition symbol parameter limits min. typ. max. ? ? ? 0.1 ? ? ? ? ? ? unit electrical characteristics (t j = 25?c, unless otherwise noted) inverter part collector-emitter saturation voltage fwdi forward voltage junction-to-heat sink thermal resistance v d = v db = 15v v cin = 0v switching times v cc = 300v, v d = 15v i c = 5a, t j = 125?c inductive load (upper-lower arm) v cin = 5 ? 0v collector-emitter cut-off current v ce = v ces 2.1 2.2 1.7 0.6 0.1 0.2 1.1 0.35 ? ? 2.9 3.2 2.9 1.1 ? 0.6 2.2 1.25 1.0 10 v m s note 3 : short-circuit protection operates only at the low-arms. please select the value of the external shunt resistor such that the sc trip level is less than 8.5a 4: fault signal is outputted when the low-arm short-circuit or control supply under-voltage protective functions operate. the faul t output pulse-width t fo depends on the capacitance value of c fo according to the following approximate equation. : c fo = (12.2 5 10 -6 ) 5 t fo [f] applied between: u p , v p , w p -v nc applied between: u n , v n , w n -v nc trip level reset level trip level reset level total of v p1 -v nc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs v p1 -v nc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between v p1 -v nc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs control supply voltage control supply voltage circuit current condition symbol parameter limits v d v db i d v foh v fol v fosat f pwm t dead v sc(ref) uv dbt uv dbr uv dt uv dr t fo v th(on) v th(off) v th(on) v th(off) min. typ. max. unit control (protection) part v d = 15v, v cin = 5v v db = 15v, v cin = 5v v d = 15v, v cin = 0v v db = 15v, v cin = 0v v sc = 0v, f o circuit : 10k w to 5v pull-up v sc = 1v, f o circuit : 10k w to 5v pull-up v sc = 1v, i fo = 15ma t j 125?c, t f 100?c relates to corresponding input signal for blocking arm shoot-through. (t f 100?c) t j = 25?c, v d = 15v (note 3) fault output voltage pwm input frequency allowable deadtime short-circuit trip level supply circuit under-voltage protection t j 125?c fault output pulse width on threshold voltage off threshold voltage on threshold voltage off threshold voltage c fo = 22nf (note 4) h-side l-side 15.0 15.0 4.25 0.50 4.95 0.50 ? 0.8 1.2 15 ? 0.5 ? ? ? ? 1.8 1.4 3.0 1.4 3.0 16.5 16.5 8.50 1.00 9.70 1.00 ? 1.2 1.8 ? ? 0.55 12.0 12.5 12.5 13.0 ? 2.0 4.0 2.0 4.0 v v ma ma ma ma v v v khz m s v v v v v ms v v
mitsubishi semiconductor PS21312 transfer-mold type insulated type aug. 1999 supply voltage control supply voltage control supply voltage control supply variation arm shoot-through blocking time pwm input frequency input on voltage input off voltage 400 16.5 16.5 1.0 ? ? mounting screw : m3 condition parameter limits mounting torque weight heat-sink flatness min. mechanical characteristics and ratings typ. max. ? ? ? e50 unit recommended 8kgcm recommended 0.78nm 8 0.78 20 ? ? ? ? 100 kgcm nm g m m v cc v d v db d v d , d v db t dead f pwm v cin(on) v cin(off) applied between p-n applied between v p1 -v nc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs for each input signal t j 125?c, t f 100?c applied between u p , v p , w p -v nc applied between u n , v n , w n -v nc condition symbol parameter limits min. typ. max. 0 13.5 13.5 e1 3 ? unit recommended operation conditions 300 15.0 15.0 ? ? 15 v v v v/ m s m s khz v v 0~0.65 4.0~5.5 note 5: (note 5) dip-ipm + heat-sink heat-sink measurement range 3mm +
mitsubishi semiconductor PS21312 transfer-mold type insulated type aug. 1999 ho dip-ipm in com u out v out w out v no cfo gnd fo w n v n u n v cc hvic 3 hvic 2 hvic 1 lvic cfo cin cin n w v u p v s v b v cc ho in com v s v b v cc ho in com v s v b v cc fo w n v n u n w p v p u p v nc v n1 v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb v no(nc) fig. 4 the dip-ipm internal circuit * note: the igbts gates and the hvics com terminals are connected to the dummy pins (not shown in figure 4).
mitsubishi semiconductor PS21312 transfer-mold type insulated type aug. 1999 fig. 5 timing charts of the dip-ipm protective functions [a] short-circuit protection (lower-arms only) (for the external shunt resistance and cr connection, please refer to fig. 3.) a1. normal operation : igbt on and carrying current. a2. short-circuit current detection (sc trigger). a3. igbt gate interrupt. a4. igbt turns off. a5. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a6. input h : igbt off state. a7. input l : igbt on state, but during the f o active signal the igbt doesn?t turn on. a8. igbt off state. [b] under-voltage protection (n-side, uv d ) a1. normal operation : igbt on and carrying current. a2. under-voltage trip (uv dt ). a3. igbt off inspite of control input condition. a4. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a5. under-voltage reset (uv dr ). a6. normal operation : igbt on and carrying current. note : the cr time constant safe guards against erroneous sc fault signals resulting from di/dt generated voltages when the igbt turn s on. the optimum setting for the cr circuit time constant is 1.5~2.0 m s. fault output fo sense voltage of the shunt resistance sc reference voltage cr circuit time constant delay ( * note) output current ic(a) internal igbt gate protection circuit state lower-arms control input a5 a8 a4 a3 a1 a2 sc reset set a7 a6 fault output fo (n-side only) output current ic(a) control supply voltage v d protection circuit state control input a6 a1 a3 a5 a2 reset uv dt uv dr set a4
mitsubishi semiconductor PS21312 transfer-mold type insulated type aug. 1999 [c] under-voltage protection (p-side, uv db ) a1. control supply voltage rises : after the voltage level reachs uv dbr , the circuits start to operate when the next input is applied. a2. normal operation : igbt on and carrying current. a3. under-voltage trip (uv dbt ). a4. igbt off inspite of control input condition (there is no f o signal output). a5. under-voltage reset (uv dbr ). a6. normal operation : igbt on and carrying current. fig. 6 recommended cpu i/o interface circuit note : rc coupling at each input (parts shown dotted) may change depending on the pwm control scheme used in the application and on the wiring impedance of the application?s printed circuit board. fault output fo output current ic(a) control supply voltage v db protection circuit state control input a6 a1 a2 a4 a5 a3 reset uv dbt uv dbr set reset high-level (no fault output) cpu 4.7k w 5.1k w 5v line 1nf 1nf u p ,v p ,w p ,u n ,v n ,w n v nc (logic) fo dip-ipm
mitsubishi semiconductor PS21312 transfer-mold type insulated type aug. 1999 fig. 7 typical dip-ipm application circuit example note 1 : to prevent the input signals oscillation, an rc coupling at each input is recommended, and the wiring of each input should be a s short as possible. (less than 2cm) 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu terminals without any opto -coupler or transformer isolation is possible. 3: f o output is open collector type. this signal line should be pulled up to the positive side of the 5v power supply with approxima tely 5.1k w resistance. 4: f o output pulse width should be decided by connecting an external capacitor between cfo and v nc terminals (c fo ). (example : c fo = 22 nf ? t fo = 1.8 ms (typ.)) 5: each input signal line should be pulled up to the positive side of the 5v power supply with approximately 4.7k w resistance (other rc coupling circuits at each input may be needed depending on the pwm control scheme used and on the wiring impedances of the system?s printed circuit board). approximately a 0.22~2 m f by-pass capacitor should be used across each power supply connection terminals. 6: to prevent errors of the protection function, the wiring of a, b, c should be as short as possible. 7: in the recommended protection circuit, please select the r 1 c 5 time constant in the range of 1.5~2 m s. 8: each capacitor should be put as nearby the terminals of the dip-ipm as possible. 9: to prevent surge destruction, the wiring between the smoothing capacitor and the p&n1 terminals should be as short as possible. ap- proximately a 0.1~0.22 m f snubber capacitor between the p&n1 terminals is recommended. ho ho dip-ipm c1: tight tolerance temp - compensated electrolytic type; c2,c3: 0. 22~2 m f r - category ceramic capacitor for noise filtering (note : the capacitance value depends on the pwm control used in the applied system.) c3 c3 c3 c3 c2 c2 c2 c1 c1 c1 ho in in 15v line 5v line 5v line in com com com u out v out w out v no cfo gnd f o w n v n v cc c b a c4(c fo ) cfo r1 c5 shunt resistance cin cin n1 n w v u p v s v s v s v b v b v b v cc v cc v cc fo w n v n u n u n w p v p u p v nc v n1 v p1 v p1 v p1 v wfs v vfs v ufs v wf v vfb v ufb m for detailed description of the bootstrap circuit construction, please contact mitsubishi electric c p u u n i t the long wiring of gnd might generate noise on input signals and cause igbt drive malfunction. if this wiring is too long, the sc level fluctuation might be large and cause sc malfunction. if this wiring is too long, it might cause sc malfunction.
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